Simulates a pipelined, superscalar, out of order processor with forwarding. Includes a variety of flags to toggle features on/off, to test and benchmark the program and to give different levels of verbose reporting. I Conducted three experiments to measure improvements in cycle count, cache misses etc.
A slideshow which accompanied a 10 minute presentation of my work, describing the features I had implemented and the results of the experiments I ran to prove the features' capabilities.